Contributor: Kenneth Yun
3D v3.02, Mixed Asynchronous / Synchronous Synthesis Tool
Extended-burst-mode Specification (cf: ICCAD'93 "Unifying
Synchronous/Asynchronous State Machine Synthesis" by Yun and Dill)
Range of specifiable behavior:
1. Restricted multiple-input change (input burst) with don't-care
2. Input choices based on sampling possibly glitchy signals
Target implementation is a combinational circuit with both primary
outputs and state variables fed back.
1. Two-level PLA description of outputs and state variables
2. Verilog netlist using a customizable CMOS standard cell/gate array
1. The 3D tools makes use of Steve Nowick's exact logic minimizer
(firstname.lastname@example.org) to generate minimized logic equations. An
alternative combinational logic minimizer based on BDD
descriptions are under investigation (ICCAD'94).
2. An algebraic technology mapper (included in the distribution)
generates a Verilog netlist from each two-level logic equation.
The CMOS library that comes with the mapper is easily
Bounded wire delay model
CONNECTION WITH OTHER TOOLS:
The 3D tool has been incorporated as a part of a larger asynchronous
synthesis system called STETSON available from HP Labs.
3D v3.13 can be obtained by following the links from
papers (ICCAD'93, EDAC'93, ICCAD'92, ICCD'92) are also available at the
Kenneth Y. Yun
Stanford, CA 94305