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I am currently investigating new tools for the design of asynchronous circuits.
Based on the Balsa asynchronous synthesis framework, my research led to:
- Breeze-sim: a Breeze (Balsa intermediate handshake circuit format) simulator designed for speed, for simulating large Balsa designs such as the SPA asynchronous ARM processor.
A visualisation/debugging system for Balsa, intended to:
- render the handshake circuit graph and provide a navigation interface,
- map multiple sources onto each other, for navigating between different formats easily (e.g. jumping through: Balsa statement -> generated Breeze handshake component -> synthesised Verilog element -> vcd trace events),
- animate simulation events on top of the handshake graph,
- provide debugging functionalities specific to asynchronous problems such as deadlocks and meta-stability.
- GALAXY/AsipIDE/GALSA/Balsamics: a system-level design tool for describing GALS (Globally Asynchronous, Locally Synchronous) systems. This is my current research topic.