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AsipIDE GALS Design and Co-Simulation Framework
Bringing together design and simulation tools in a GALS hardware-software-FPGA co-debugging flow
Developed as part of the EU-funded Framework 7 GALAXY project.
Keywords: GALS Design Tools, GALS EDA Tools, Galaxy-IDE, AsipIDE, ASIP-IDE
AsipIDE is a graphical design front-end able to control any existing compilation, simulation or synthesis tool to form complete design flows.
In addition to providing hierarchical and multi-abstraction design entry, input files can be generated or converted to the required formats, co-simulation is possible, and output files such as trace files can be analysed for debugging within the graphical environment.
Our framework also encourages an iterative design style where modules are iteratively refined from high-level software simulation to hardware circuits.
It is based on the following key ideas:
- Allowing components at any levels of abstraction and any description languages to be simulated seamlessly together, with an automatic generation of the co-simulation interfaces.
- Being an extensible platform allowing the integration of any existing tools.
- Open-source tools, in particular, can be brought together as complete tool flows.
- Thanks to the integration of University of Bologna's XPipes, networks on chip can also be graphically designed, inspected and optimised.
- Guiding users in the design of GALS systems, by automating the suggestion and placement of GALS adapters, and by making debugging and optimizations through simulation easier thanks to advanced visualization techniques.
Read Section 2 of the manual for installation details.
Submit a bug
Our Bugzilla bug report system is available at http://solem.cs.man.ac.uk/.
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