School of Computer Science Intranet
The FIRE Asynchronous Artificial Neural Network Project is funded jointly by the EPSRC and Cogniscience. The aim is to develop a hardware implementation of an artificial neural network using asynchonous digital technology. The heart of the system is the proposed FIRE1 chip, a 256-neuron processing sub-system designed to allow multiple chips to be connected to form an artifical neural network of arbitrary size. The neurons communicate asynchronously via pulses generated using integrate and fire logic.
Current work is concentrating on finding a suitable neural learning algorithm. One approach is based on the sparse distributed memory model proposed by Kanerva but using a N-of-M coded information system which leads to higher storage density for a given read back reliability. N-of-M codes have a word length of M bits of which just N are set and M-N are clear. Thus, in a group of M neurons which carry the code, exactly N will fire otherwise the code is invalid. This property enables good error recovery and makes the system relatively insensitive to noise and other sources of error. The resulting neural system is biologically plausible, using only unipolar weights, and can be approximated by neural systems with sparse, random synaptic connections.
On the hardware side we are devloping a Kanerva-style neural memory model using N-of-M codes based on the Altera Excalibur development board. The main active components on the board are an embedded ARM processor and a programmable gate array (PGA). The PGA is programmed mainly as an array of spiking neural processing elements under the control of a software program executing on the ARM processor. The board currently can hold around 1500 neural elements but the design is intended to be scalable and we are aiming eventually to simulate more than a million neurons.
The Group is led by Steve Furber with the following group members: