The Advanced Processors Technologies Research Group

APT Group Publications by Author

These are in reverse chronological order. Theses are emphasized.

Steve Furber

• Power-efficient simulation of detailed cortical microcircuits on SpiNNaker
• Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System
• Managing a Massively-Parallel Resource-Constrained Computing Architecture
• Population-Based Routing in the SpiNNaker Neuromorphic Architecture
• Visualising Large-Scale Neural Network Models in Real-Time
• Real Time On-Chip Implementation of Dynamical Systems with Spiking Neurons
• Event-Driven MLP Implementation on Neuromimetic Hardware
• SpiNNaker: A Multi-Core System-on-Chip for Massively-Parallel Neural Net Simulation
• Overview of the SpiNNaker system architectur
• The Impact of Technology Scaling in the SpiNNaker Chip Multiprocessor
• An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
• A hierarchical configuration system for a massively parallel neural hardware platform.
• "Serial" Effects in Parallel Models of Reading
• A forecast-based STDP rule suitable for neuromorphic implementation
• Scalable Communications for a Million-Core Neural Processing Architecture
• SpiNNaker: Design and Implementation of a GALS Multi-Core System-on-Chip
• Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis
• Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware
• Event-Driven SpiNNaker Simulation
• A Novel Programmable parallel CRC Circuit
• An Event-Driven Model for the SpiNNaker Virtual Synaptic Channel
• A forecast-based biologically-plausible STDP learning rule
• Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
• Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric
• Distributed Configuration of Massively-Parallel Simulation on SpiNNaker Neuromorphic Hardware
• Representing and Decoding Rank Order Codes Using Polychronization in a Network of Spiking Neurons
• Maintaining real-time synchrony on SpiNNaker
• A General-Purpose Model Translation System for a Universal Neural Chip
• Interfacing Real-Time Spiking I/O with the SpiNNaker neuromimetic architecture
• STDP pattern onset learning depends on background activity
• Modeling Spiking Neural Networks on SpiNNaker
• A Novel Programmable parallel CRC Circuit
• Biologically Inspired Means for Rank-Order Encoding Images: A Quantitative Analysis
• Algorithm and Software for Simulation of Spiking Neural Networks on the Multi-Chip SpiNNaker System
• Implementing Spike-Timing-Dependent Plasticity on SpiNNaker Neuromorphic Hardware
• The Leaky Integrate-and-Fire Neuron: A Platform for Synaptic Model Exploration on the SpiNNaker Chip
• Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware
• SpiNNaker: Effects of Traffic Locality and Causality on the Performance of the Interconnection Network
• Scalable Event-Driven Native Parallel Processing: The SpiNNaker Neuromimetic System
• Efficient Parallel Implementation of Multilayer Backpropagation Network on Torus-connected CMPs
• A communication infrastructure for a million processor machine
• The Amulet chips: Architectural Development for Asynchronous Microprocessors
• Adaptive Admission Control on the SpiNNaker MPSOC
• Biologically-Inspired Massively-Parallel Architectures - computing beyond a million processors
• A Multicast Routing Scheme for a Universal Spiking Neural Network Architecture
• Understanding the Interconnection Network of SpiNNaker
• A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
• Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric
• Optimal Connectivity In Hardware-Targetted MLP Networks
• Evaluating Rank-order Code Performance Using A Biologically Derived Retinal Model
• A Universal Abstract-Time Platform for Real-Time Neural Networks
• Fault-Tolerant Delay-Insensitive Inter-Chip Communication
• A Programmable Adaptive Router for a GALS Parallel System
• System Level Modelling for SpiNNaker CMP System
• SpiNNaker: The design automation problem
  
• The Deferred Event Model for Hardware-Oriented Spiking Neural Networks
  
• An Admission Control System for QoS Provision on a Best-effort GALS Interconnect
  
• Virtual Synaptic Interconnect Using an Asynchronous Network-on-Chip
  
• SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor
  
• Efficient Modelling of Spiking Neural Networks on a Scalable Chip Multiprocessor
  
• An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator
  
• The Future of Computer Technology and its Implications for the Computer Industry
  
• A GALS Infrastructure for a Massively Parallel Multiprocessor
  
• Neural systems engineering
  
• Maximising Information Recovery from Rank-Order Codes
  
• Sparse Distributed Memory using Rank-Order Neural Codes
  
• The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing.
  
• Information Recovery from Rank-Order Encoded Images
  
• On-Chip and Inter-Chip networks for Modelling Large-Scale Neural Systems.
  
• High-Performance Computing for Systems of Spiking Neurons.
  
• Future Trends in SoC Interconnect.
  
• The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics.
  
• A spiking neural sparse distributed memory implementation for learning and predicting temporal sequences.
  
• An associative memory for the on-line recognition and prediction of temporal sequences.
  
• A system for transmitting a coherent burst of activity through a network of spiking neurons.
  
• A low power embedded dataflow coprocessor.
  
• Future Trends in SoC Interconnect
  
• An Asynchronous On-Chip Network Router with Quality-of-Service (QoS) Support.
• A Sparse Distributed Memory based upon N-of-M Codes.
• The Design of a Low-Power Asynchronous Multiplier.
• Minimizing the Power Consumption of an Asynchronous Multiplier.
• Design and Analysis of a Self-Timed Duplex Communication System.
• The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip
• An Asynchronous Ternary Logic Signalling System
• An asynchronous low latency arbiter for Quality of Service (QoS) applications.
• Designing Robust Asynchronous Circuits
• An asynchronous copy-back cache architecture
• Quality of Service (QoS) for Asynchronous On-Chip Networks
• Prototyping a Digital Neural Network System-on-Chip using an Altera Excalibur Device
• A Low-Power Asynchronous Multiplier
• An Investigation into the Security of Self-timed Circuits
• Delay-Insensitive, Point-to-Point Interconnect using m-of-n codes
• CHAIN: A Delay Insensitive CHip Area INterconnect
• An Asynchronous Victim Cache
• Validating the AMULET Microprocessors
• Applying asynchronous techniques to a Viterbi decoder design
• Power Management in the AMULET Microprocessors
• Delay Insensitive System-on-Chip Interconnect Uning 1-of-4 Data Encoding
• A Low-Power Self-Timed Viterbi Decoder
• A Novel Area-Efficient Binary Adder
• AMULET3: a 100 MIPS Asynchronous Embedded Processor
• A Power-Efficient Duplex Communication System
• An Asynchronous Viterbi Decoder
• MARBLE: An Asynchronous On-Chip Macrocell Bus
• On-chip timing reference for self-timed microprocessor
• Kicking out the Clock
• AMULET3i - an Asynchronous System-on-Chip
• The design of the control circuit for an asynchronous instruction prefetch unit using signal transition graphs
• AMULET3 Revealed
• AMULET2e: An Asynchronous Embedded Controller
• The Design of an Asynchronous VHDL Synthesizer
• Asynchronous Macrocell Interconnect using MARBLE
• Asynchronous Embedded Control
• Modelling and Simulation of Asynchronous Systems using the LARD Hardware Description Language
• AMULET3: A High-Performance Self-Timed ARM Microprocessor
• Behavioural Modelling of Asynchronous Systems for Power and Performance Analysis
• AMULET1: An Asynchronous ARM Microprocessor
• Built-In Self-Test Design of Micropipelines
• AMULET2e: An Asynchronous Embedded Controller
• Britain needs Manufacturing
• Asynchronous Logic.
• Breaking Step - the Return of Asynchronous Logic.
• Design for Testability of an Asynchronous Adder.
• Dynamic Logic in Four-Phase Micropipelines.
• Four-Phase Micropipeline Latch Control Circuits.
• AMULET2e.
• Scan testing of asynchronous sequential circuits.
• Scan testing of micropipelines.
• Designing Asynchronous Sequential Circuits for Random Pattern Testability.
DOI-Link
• Designing C-elements for Testability.
• AMULET1: A Micropipelined ARM
• Transforming Architectural Models Into High Performance Concurrent Implementations
• The Design and Evaluation of an Asynchronous Microprocessor
• Breaking Step - the Return of Asynchronous Logic.
• AMULET1 - An Asynchronous ARM Processor.
• Computing without Clocks.
• A Micropipelined ARM
• Register Locking in an Asynchronous Microprocessor

Jim Garside

• Overview of the SpiNNaker system architecture
• Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches
• Overview of the SpiNNaker system architecture
• An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
• Scalable Communications for a Million-Core Neural Processing Architecture
• The Amulet chips: Architectural Development for Asynchronous Microprocessors
• Fault-Tolerant Delay-Insensitive Inter-Chip Communication
• A Programmable Adaptive Router for a GALS Parallel System
• Design and implementation of an energy efficient, parallel, asynchronous DSP
• Sensitive Registers: a Technique for Reducing the Fetch Bandwidth in Low-Power Microprocessors
• Modernisation of Teaching in Embedded Systems Design - An International Collaborative Project
• A Low-Power Processor Architecture Optimized for Wireless Devices.
• A Quasi-Delay-Insensitive Method to Overcome Transistor Variation.
• Energy efficient functional unit for a parallel asynchronous DSP.
• An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm
• A CAM with mixed serial-parallel comparison for use in low energy caches
• Designing Robust Asynchronous Circuits
• An asynchronous copy-back cache architecture
• Early Output Logic using Anti-Tokens
  
• SPA - A Secure Amulet Core for Smartcard Applications
• Adaptive Pipeline Structures for Speculation Control
• Adaptive Pipeline Depth Control for Processor Power-Management
• An Asynchronous Victim Cache
• An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks
• SPA - A Synthesisable Amulet Core for Smartcard Applications
• A Comparative Power Analysis of an Asynchronous Processor
• Power Management in the AMULET Microprocessors
• AMULET3i Cache Architecture
• A Practical Comparison of Asynchronous Design Styles
• AMULET3: a 100 MIPS Asynchronous Embedded Processor
• AMULET3i - an Asynchronous System-on-Chip
• AMULET3i - an Asynchronous System-on-Chip
• AMULET3 Revealed
• Memory Faults in Asynchronous Microprocessors
• Reconfigurable Latch Controllers for Low Power Asynchronous Circuits
• AMULET2e: An Asynchronous Embedded Controller
• Asynchronous Embedded Control
• Re-configurable Latch Controllers for Low Power Asynchronous Circuits
• AMULET3: A High-Performance Self-Timed ARM Microprocessor
• AMULET1: An Asynchronous ARM Microprocessor
• A Result Forwarding Mechanism for Asynchronous Pipelined Systems
• AMULET2e: An Asynchronous Embedded Controller
• The AMULET2e Cache System.
• AMULET2e.
• AMULET2e.
• A Comparison of Power Consumption in some CMOS Adder Circuits
• A Cache Line Fill Circuit for a Micropipelined Asynchronous Microprocessor
• AMULET1: A Micropipelined ARM
• The Design and Evaluation of an Asynchronous Microprocessor
• A CMOS VLSI Implementation of an Asynchronous ALU
• A Micropipelined ARM
• Register Locking in an Asynchronous Microprocessor

David R.Lester

• Overview of the SpiNNaker system architecture
• The World's Shortest Correct Exact Real Arithmetic Program?
• Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware
• Spiking Neural PID Controllers
• A monadic approach to automated reasoning for Bluespec SystemVerilog
  Innovations in Systems and Software Engineering
• Interfacing Real-Time Spiking I/O with the SpiNNaker neuromimetic architecture
• A communication infrastructure for a million processor machine
• High Accuracy Machine-Efficient Chebyshev Approximations: an Application to Spectral Methods for Sobolev Spaces
  
• SpiNNaker: The design automation problem
  
• SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor
  
• Computable Function Representation Using Effective Chebyshev Polynomial
• Stochastic Formal Methods: An Application to Accuracy of Numeric Software
• FUNCTIONAL PEARL: Enumerating the rationals
• Using PVS to validate the Algorithms of an Exact Arithmetic
• A Constructive Algorithms for finding the Exact Roots of Polynomials with Computable Real Coefficients
• A Survey of Exact Arithmetic Implementations
• Effective Continued Fractions
• Exact Arithmetic and the Korteweg-de Vries Equation
• The Correctness of an Implementation of Exact Arithmetic
• Validating the Correctness of an Exact Arithmetic Package
• Towards a machine-checked congruence for exact arithmetic

Mikel Lujan

• Reservation-based Network-on-Chip timing models for large-scale architectural simulation
• Architectural Support for Exploiting Fine Grain Parallelism
• A case for Exiting a Transaction in the Context of Hardware Transactional Memory.
• SnCTM: Reducing False Transaction Aborts by Adaptively Changing the Source of Conflict Detection
• Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
• The Economics of Garbage Collection
• Scalable Object-Aware Hardware Transactional Memory
• Clustering JVMs with Software Transactional Memory Support.
• Improving Performance by Reducing Aborts in Hardware Transactional Memory.
• Modeling Spiking Neural Networks on SpiNNaker
• Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware
• SpiNNaker: Effects of Traffic Locality and Causality on the Performance of the Interconnection Network
• Efficient Parallel Implementation of Multilayer Backpropagation Network on Torus-connected CMPs
• On the Performance of Contention Managers for Complex Transactional Memory Benchmarks
• Understanding the Interconnection Network of SpiNNaker
• Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric
• Profiling Transactional Memory Applications.
• Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
• An Object-Aware Hardware Transactional Memory System
• Adaptive Loop Tiling for a Multi-cluster CMP
• Speculative Parallelization - Eliminating the Overhead of Failure
• A Study of a Transactional Parallel Routing Algorithm
• Towards Intelligent Analysis Techniques for Object Pretenuring

Luis Plana

• Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System
• SpiNNaker: A Multi-Core System-on-Chip for Massively-Parallel Neural Net Simulation
• Overview of the SpiNNaker system architecture
• An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
• A hierarchical configuration system for a massively parallel neural hardware platform.
• Scalable Communications for a Million-Core Neural Processing Architecture
• SpiNNaker: Design and Implementation of a GALS Multi-Core System-on-Chip
• Event-Driven SpiNNaker Simulation
• An Event-Driven Model for the SpiNNaker Virtual Synaptic Channel
• Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
• Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric
• Description-level optimisation of synthesisable asynchronous circuits.
• Asynchronous Data-Driven Circuit Synthesis
• Modeling Spiking Neural Networks on SpiNNaker
• Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware
• SpiNNaker: Effects of Traffic Locality and Causality on the Performance of the Interconnection Network
• Scalable Event-Driven Native Parallel Processing: The SpiNNaker Neuromimetic System
• Efficient Parallel Implementation of Multilayer Backpropagation Network on Torus-connected CMPs
• A communication infrastructure for a million processor machine
• System-on-Chip Design and Implementation
• Adaptive Admission Control on the SpiNNaker MPSOC
• A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
• Understanding the Interconnection Network of SpiNNaker
• Asynchronous Data-Driven Circuit Synthesis
• A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
• Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric
• A Universal Abstract-Time Platform for Real-Time Neural Networks
• Fault-Tolerant Delay-Insensitive Inter-Chip Communication
• System Level Modelling for SpiNNaker CMP System
• SpiNNaker: The design automation problem
  
• An Admission Control System for QoS Provision on a Best-effort GALS Interconnect
  
• Automatic Compilation of Data-Driven Circuits
  
• SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor
  
• An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator
  
• Performance-driven syntax-directed synthesis of asynchronous processors.
• A GALS Infrastructure for a Massively Parallel Multiprocessor.
• Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance.
• The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip
• SPA - A Secure Amulet Core for Smartcard Applications
• An Investigation into the Security of Self-timed Circuits
• SPA - A Synthesisable Amulet Core for Smartcard Applications

Steve Temple

• SpiNNaker: A Multi-Core System-on-Chip for Massively-Parallel Neural Net Simulation
• Overview of the SpiNNaker system architecture
• An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
• Scalable Communications for a Million-Core Neural Processing Architecture
• SpiNNaker: Design and Implementation of a GALS Multi-Core System-on-Chip
• Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric
• Algorithm and Software for Simulation of Spiking Neural Networks on the Multi-Chip SpiNNaker System
• The Amulet chips: Architectural Development for Asynchronous Microprocessors
• A GALS Infrastructure for a Massively Parallel Multiprocessor
  
• Neural systems engineering
  
• On-Chip and Inter-Chip networks for Modelling Large-Scale Neural Systems.
  
• High-Performance Computing for Systems of Spiking Neurons.
  
• A Sparse Distributed Memory based upon N-of-M Codes.
• SPA - A Secure Amulet Core for Smartcard Applications
• SPA - A Synthesisable Amulet Core for Smartcard Applications
• A Comparative Power Analysis of an Asynchronous Processor
• Power Management in the AMULET Microprocessors
• On-chip timing reference for self-timed microprocessor
• AMULET3i - an Asynchronous System-on-Chip
• AMULET2e: An Asynchronous Embedded Controller
• Asynchronous Embedded Control
• AMULET1: An Asynchronous ARM Microprocessor
• AMULET2e: An Asynchronous Embedded Controller
• AMULET2e.
• The Design and Evaluation of an Asynchronous Microprocessor

Alexander Rast

• Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware
• An Event-Driven Model for the SpiNNaker Virtual Synaptic Channel
• A forecast-based biologically-plausible STDP learning rule
• Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
• Maintaining real-time synchrony on SpiNNaker
• A General-Purpose Model Translation System for a Universal Neural Chip
• Interfacing Real-Time Spiking I/O with the SpiNNaker neuromimetic architecture
• Algorithm and Software for Simulation of Spiking Neural Networks on the Multi-Chip SpiNNaker System
• Implementing Spike-Timing-Dependent Plasticity on SpiNNaker Neuromorphic Hardware
• The Leaky Integrate-and-Fire Neuron: A Platform for Synaptic Model Exploration on the SpiNNaker Chip
• Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware
• Scalable Event-Driven Native Parallel Processing: The SpiNNaker Neuromimetic System
• Efficient Parallel Implementation of Multilayer Backpropagation Network on Torus-connected CMPs
• Optimal Connectivity In Hardware-Targetted MLP Networks
• A Universal Abstract-Time Platform for Real-Time Neural Networks

Linda Brackenbury

• Early stopping turbo decoders: a high-throughput, low-energy bit-level approach and implementation
• System-on-Chip Design and Implementation
• Pre-processing of Convolutional Codes for Reducing Decoding Power Consumption
• No-Handshake Asynchronous Survivor memory Unit for a Viterbi Decoder
• Lowering power in an experimental RISC processor
• Design and implementation of an energy efficient, parallel, asynchronous DSP
• Energy efficient functional unit for a compute-intensive asynchronous DSP.
• Energy efficient functional unit for a parallel asynchronous DSP.
• An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm
• Design of asynchronous function unit & software development tools for a low-power DSP.
• Functional Unit for Low-Power DSP Architecture
• CADRE: an Asynchronous Embedded DSP for Mobile Phone Applications
• Low power asynchronous DSP for digital mobile phones.
• Applying asynchronous techniques to a Viterbi decoder design
• Combining SOI Technology and Asynchronous Design Techniques for Power Reduction.
• A simulation study to quantify the advantages of silicon-on-insulator (SOI) technology for low power
• CADRE: A Low-Power, Low-EMI DSP Architecture for Digital Mobile Phones
• A Low-Power Self-Timed Viterbi Decoder
• Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank
• The Optical Encryption of Digital Data
• Exploiting Asynchronous Self-Timed Techniques on SOI Technology for Low Power
• An Asynchronous Viterbi Decoder
• A low-power asynchronous DSP architecture for digital mobile phone chipsets
• An Instruction Buffer for a Low-Power DSP
• Power reduction in self-timed circuits using early-open latch controllers
• Reconfigurable Latch Controllers for Low Power Asynchronous Circuits
• Re-configurable Latch Controllers for Low Power Asynchronous Circuits
• Optical solution to the Lee algorithm by use of symbolic substitution
• Differential register bank design for self timed differential bipolar technology
• Design and modelling of a high performance differential bipolar self-timed microprocessor
• Transforming Architectural Models Into High Performance Concurrent Implementations

Doug Edwards

• Survey of asynchronous networks-on-chip. (In Chinese)
• Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches
• Routing of Asynchronous Clos Networks
• Indicating combinational logic decomposition
• Asynchronous spatial division multiplexing router
• Description-level optimisation of synthesisable asynchronous circuits.
• Asynchronous Data-Driven Circuit Synthesis
• An Asynchronous Routing Algorithm for Clos Networks
• A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
• Self-Timed Realization of Combinational Logic
• M-of-N Code Decomposition for Indicating Combinational Logic
• Computation Reduction for Statistical Analysis of the Effect of nano-CMOS Variability on Asynchronous Circuits
• Integrated Design Environment for Reconfigurable HPC
• A low latency wormhole router for asynchronous on-chip networks.
• LLA: A low-latency asynchronous control with applications
• Building Asynchronous Routers with Independent Sub-Channels
• A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
• Heterogeneously encoded dual-bit self-timed adder
• Teak: A Token-Flow Implementation for the Balsa Language
• HPAP: A High Performance Control Circuit for Asynchronous Pipeline Design
• Asynchronous Data-Driven Circuit Synthesis
• Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks
• Dual-Sum Single-Carry Self-Timed Adder Designs
• Adaptive Stochastic Routing in Fault-tolerant On-chip Network
• Forward and Backward Guarding in Early Output Logic
• Self-Timed Full Adder Designs based on Hybrid Input Encoding
• Power, Delay and Area Efficient Self-Timed Multiplexer and Demultiplexer Designs
• A delay efficient robust self-timed full adder
• Automatic Compilation of Data-Driven Circuits
• Efficient realization of strongly indicating function blocks
• A new design technique for weakly indicating function blocks
• Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems
• Performance-driven syntax-directed synthesis of asynchronous processors
• CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse
• Speeding Up Verilog Gate-Level Simulation with Bi-Partitioning
• Low power synthesis of XOR-XNOR intensive combinational logic
• Synthesis of Power and Delay optimized NIG structures
• A Framework for Distributed Simulation for Asynchronous Handshake Circuits
• Synthesising Heterogeneously Encoded Systems
• Test Pattern Generation and Partial-Scan Methodology for an Asynchronous SoC Interconnect.
• Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance.
• Software Visualisation Techniques Adapted and Extended for Asynchronous Hardware Design.
• DiSigncryption: An Integration of Agent-based Signature Delegation with Distributed Reputation Management Scheme.
• Asynchronous On-Chip Networks.
• Efficient Synthesis of Speed Independent Combinational Logic Circuits.
• Synthesis of Asynchronous Circuits using Early Data Validity.
• Adding Testability to an Asynchronous Interconnect for GALS SoC.
• Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits
• Simulation and Analysis of Synthesised Asynchronous Circuits
• Delay-Insensitive, Point-to-Point Interconnect using m-of-n codes
• A Burst-Mode Oriented Back-End for the Balsa Synthesis System
• Balsa: An Asynchronous Hardware Synthesis Language
• Towards a Framework for the Distributed Simulation of Asynchronous Hardware
• Synthesising an asynchronous DMA controller with Balsa
• AMULET3: a 100 MIPS Asynchronous Embedded Processor
• The Balsa Asynchronous Circuit Synthesis System
• AMULET3i - an Asynchronous System-on-Chip
• Compiling the Language Balsa to Delay Insensitive Hardware.
• Tools for Validating Asynchronous Digital Circuits
• Logic for Low Power Consumption in Asynchronous Circuits
• Pitfalls in Asynchronous Design.

Chris Kirkham

• Clustering JVMs with Software Transactional Memory Support.
• Improving Performance by Reducing Aborts in Hardware Transactional Memory.
• On the Performance of Contention Managers for Complex Transactional Memory Benchmarks
• Profiling Transactional Memory Applications.
• Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
• Constraint Based Optimization of Stationary Fields
• Exploiting the Correspondence between Micro Patterns and Class Names
• Adaptive Loop Tiling for a Multi-cluster CMP
• Dynamic Analysis of Java Program Concepts for Visualization and Profiling
• Ranked reservoir sampling: an extension to the reservoir sampling algorithm
• A Study of a Transactional Parallel Routing Algorithm
• Optimizing Chip Multiprocessor Work Distribution using Dynamic Compilation
• Dynamic Analysis of Program Concepts in Java
• Supporting Higher Order Virtualization
• Loop Parallelisation for the Jikes RVM
• An Automatic Runtime DOALL Loop Parallelisation Optimization for Java.
• JikesNODE and PearColator: A Jikes RVM Operating System and Legacy Code Execution Environment.
• A System for Running Loop Optimisation in the Jikes RVM.
• Exploiting Implicit Parallelism in Functional Programs with SLAM.

Alasdair Rawsthorne

• Consistent Windowing Interfaces in Distributed Heterogeneous Environments.
• Exploiting Hardware Resources: Register Assignment across Method Boundaries

Ian Watson

• Architectural Support for Exploiting Fine Grain Parallelism
• A case for Exiting a Transaction in the Context of Hardware Transactional Memory.
• SnCTM: Reducing False Transaction Aborts by Adaptively Changing the Source of Conflict Detection
• Scalable Object-Aware Hardware Transactional Memory
• Clustering JVMs with Software Transactional Memory Support.
• Improving Performance by Reducing Aborts in Hardware Transactional Memory.
• On the Performance of Contention Managers for Complex Transactional Memory Benchmarks
• Profiling Transactional Memory Applications.
• Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
• An Object-Aware Hardware Transactional Memory System
• Constraint Based Optimization of Stationary Fields
• Adaptive Loop Tiling for a Multi-cluster CMP
• Intelligent selection of application-specific garbage collectors
• A Study of a Transactional Parallel Routing Algorithm
• Towards Intelligent Analysis Techniques for Object Pretenuring
• Optimizing Chip Multiprocessor Work Distribution using Dynamic Compilation
• Branch Prediction with Bayesian Networks
• Supporting Higher Order Virtualization
• Loop Parallelisation for the Jikes RVM
• An Automatic Runtime DOALL Loop Parallelisation Optimization for Java.
• A RISC Hardware Platform for Low Power Java.
• Exploiting Implicit Parallelism in Functional Programs with SLAM.
• A two dimensional vector architecture for multimedia.
• Dynamic Java threads on the Jamaica single-chip multiprocessor.
• VLSI architecture using lightweight threads (VAULT) - choosing the instruction set architecture.

John V Woods

• Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric
• The Amulet chips: Architectural Development for Asynchronous Microprocessors
• Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric
• System Level Modelling for SpiNNaker CMP System
• Efficient Modelling of Spiking Neural Networks on a Scalable Chip Multiprocessor
• AMULET3i - an Asynchronous System-on-Chip
• AMULET1: An Asynchronous ARM Microprocessor
• Occam: An Asynchronous Hardware Description Language?
• Simulating Asynchronous Architectures on Transputer Networks.
• Timing Verification for Asynchronous Design.
• Investigations into Micropipeline Latch Design Styles.
• Dealing with Time Modelling Problems in Parallel Models of Asynchronous Computer Architectures.
• Analysing the Timing Error in Distributed Simulations of Asynchronous Computer Architectures.
• AMULET1: A Micropipelined ARM
• Building Parallel Distributed Models for Asynchronous Computer Architectures
• Distributed Simulation of Asynchronous Computer Architectures: The Program Driven Conservative Approach
• The Design and Evaluation of an Asynchronous Microprocessor
• A Micropipelined ARM
• Register Locking in an Asynchronous Microprocessor