School of Computer Science Intranet
D. Donaghy, L. Brackenbury and S. Hall
The superior leakage current characteristics of SOI enables the threshold voltage to be lowered enhancing the current drive properties of SOI technology and enabling further power reduction without loss of performance. At the architectural level of design, the adoption of asynchronous timing rather than a global clock reduces power. Although asynchronous control tends to be larger than in synchronous systems, significant power savings should result as the clock generation drivers and distribution are consuming around one third of the power in large, complex, high performance systems.The aim of this work is to quantify the advantages of applying power efficiency strategies at both the device/technology and architectural levels of design, by taking a fixed point ripple self-timed adder implemented on SOI as a design example.