William J. Bainbridge
A shared system bus is a key feature of modern system-on-chip design methodologies. It allows the independent development of major macrocells which are then brought together in the final stages of development. The use of a synchronous bus in a synchronous design brings with it problems as a result of clock-skew across the chip and the use of many timing domains in a system. In an asynchronous system, the use of a synchronous bus would subvert many of the benefits offered by asynchronous logic such as reduced electromagnetic emissions.
This thesis describes an asynchronous system-on-chip bus which offers a solution to such problems. Existing shared-bus techniques are re-investigated in the context of an asynchronous implementation and a complete bus design is presented that has been developed for use in an asynchronous subsystem of a mixed-synchrony chip. This chip will imminently form part of one of the first commercially available products to incorporate components that use asynchronous VLSI techniques.
The split-transfer primitive, often avoided or added as an optional extension by synchronous designers, is used as the basis for the chosen bus architecture. It offers a fine-grained interleaving of bus activity and a better bus availability than would an interlocked-transfer technique as found in many synchronous alternatives. This technique is viable in an asynchronous design because of the very low arbitration latency.
Simulation results show that the proposed architecture achieves a performance comparable with synchronous buses that use similar levels of resource, whilst maintaining the benefits of the asynchronous design style.
The thesis is available in pdf form by ftp (3.1MB).