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Dependency and Exception Handling in an Asynchronous Microprocessor
David A. Gilbert
Dependency and exception handling mechanisms are an important part of modern high-performance microprocessors. In a pipelined microprocessor, dependency and exception handling require different stages of the pipeline to interact with each other to determine the current state of the processor as a whole. In a synchronous processor interactions between separate pipeline stages are managed using a global clock. Communication between non-neighbouring pipeline stages is more complex in an asynchronous microprocessor which does not have a global clock.
This thesis describes a solution to this problem in the context of a third generation asynchronous implementation of the ARM instruction set architecture. The architecture described provides powerful and efficient dependency resolution while simultaneously providing a flexible, low overhead exception handling mechanism. The mechanism provides the basis for the architecture of the AMULET3 microprocessor.
Existing exception handling and dependency resolution mechanisms are re-evaluated in the context of asynchronous implementation and the ARM architecture. The Reorder Buffer is chosen as the basis of the architecture and novel enhancements are proposed which enable its use in an asynchronous environment.
Simulation results are presented that show that the proposed architecture is significantly faster and more flexible than comparable architectures while still providing complete compatibility with the ARM instruction set architecture.