School of Computer Science Intranet
An Asynchronous ARM Compatible Memory Management Unit Design and Implementation
This thesis proposes two architectures for an asynchronous ARM compatible Memory Management Unit (MMU): a very simple Baseline Architecture which operates mainly sequentially and a pipelined Performance Architecture which uses more concurrency.
The MMU architectures are based around a proposed modified coprocessor interface which integrates the processor and coprocessor more closely than the standard ARM model and is better suited for asynchronous operation. The thesis also covers an extension to the interface which allows reordering of coprocessor instructions and out-of-order completion of coprocessor instructions, something which is not possible with the existing synchronous interface.
The Memory Management Units, as well as the necessary controlling coprocessor, were implemented using Balsa, an asynchronous hardware description language developed at the University of Manchester. The thesis explores the suitability of Balsa for the implementation of complex designs and details problems and solutions to asynchronous specific problems such as `pipeline colour', as well as solutions to MMU specific problems, such as TLB entry invalidation and coprocessor register locking.
Simulation of the synthesised transistor netlists show that both MMU designs add substantial overhead to each memory access. The faster Performance Architecture is predicted to supply instructions to a processor at a rate of around 10MHz, indicating the need for a faster Balsa backend and more investigation into asynchronous MMU architecture.
The thesis is available by ftp as GZipped PostScript (405K).